1. Field of the Invention
The present invention relates to transfer of signals through channels of a backplane, and, more specifically, to reduction of crosstalk between the channels.
2. Description of the Related Art
A terminal transferring signals in channels between circuit boards, a circuit board transferring signals in channels between circuit components, and an application specific integrated circuit (ASIC) transferring signals in channels between circuit modules are examples of typical communication applications. These communication applications may employ a backplane to couple the circuit boards/components/modules. For these communication applications, a backplane that has groups of transmit and receive channels may have the channels physically located very close to one another. For circuit board, hybrid device, and integrated circuit (IC) applications especially, as the speed of the transferred signals increases through the channels, electromagnetic effects degrade signal quality through introduced noise and background interference between the channels, sometimes referred to as “crosstalk.”
FIG. 1 shows a backplane configuration 100 illustrating coupling of signals between channels. As shown in FIG. 1, channel 1 transfers signals between modules A and B (between CH1 A and CH1 B), and channel 2 transfers signals between modules A and B (between CH2 A and CH2 B). Each signal is a differential signal transferred over a differential pair, where one of the pair is designated a positive node or terminal and the other one of the pair is a negative node or terminal. A transmit portion of channel 1 (e.g., TX of CH1 A) transfers a first signal to a receive portion of channel 1 (e.g., RX of CH1 B). Similarly, a transmit portion of channel 2 (e.g., TX of CH2 B) transfers a second signal to a receive portion of channel 2 (e.g., RX of CH2 A). Coupling 105 occurs between the first and second signals of CH1 and CH2. The terms “near end” and “far end” for a module are well known in the art and may be understood with respect to FIG. 1. Module CH1 A has as its near end the TX and RX of CH1 A, while module CH1 A has as its far end the TX and RX of CH1 B.
Near-end crosstalk (NEXT) is distortion of the signal that occurs at the near-end (the receiver) of a module. Tests by EMC/EMI specialists in many disciplines indicate that the majority of NEXT that a given receiver experiences in a multiple channel (spatial) environment is due to adjacent channel coupling from the transmitter. Far-end crosstalk (FEXT) is distortion of the signal that occurs at the far end of the module. The majority of FEXT that a channel experiences is due to common-mode imbalance. That common-mode imbalance is directly related to positive-to-negative (P-N) skew (misalignment) between the signals in the differential pair of the module's transmit portion of the channel.
The placement of backplane traces (location of leads carrying the signals in the transmit and receive portion channels) between two channels in a given package (physical circuit/backplane implementation) relates to the observed crosstalk effects. Crosstalk is generally a significant factor in observed performance in tightly packed back planes (e.g., when there is <1-mm separation between differential pairs). This placement may cause i) coupling of signals in the two channels to occur and ii) P-N common-mode imbalance to occur. In addition, crosstalk effects might not limit package size, and package parasitic terms might limit effectiveness of crosstalk reduction circuits.
Individual channels that are not integrated into a multiple-channel (spatial) environment also require crosstalk reduction, but such crosstalk reduction focuses on precise control of timing events between channels. Such precise control is severely limited when attempting to create low skew (<20 ps) control loops between separately packaged interfaces. Due to the larger physical size of an individually packaged part, crosstalk control of the prior art might not provide noticeable improvements in background noise.
Distributing high-speed clock signals (>1GHz) is desirable for enhanced performance of either high-density or high-speed integrated circuits. However, latency in the various clock signals may yield differences in timing between events on a given system-on-chip (SOC) implementation. Differences in the timing of signals may contribute to crosstalk effects, especially when differential signals are employed. This contribution to crosstalk effects arises as follows. Differential signals, when one is inverted and combined with the other, tend to cancel out noise (from, for example, coupling). If a difference in timing between the differential signals exists, the combination is imperfect and the added noise is not completely canceled. Synchronization of timing events between high-speed interfaces may reduce crosstalk effects.
In many prior art SOC designs, large portions of the ASIC operate at relatively low speed (e.g., <1 GHz) while supporting an interface to off-chip resources at relatively high speed (e.g., >1 GHz). Ordinarily, a series of dividers (e.g., divide-by-N stages) might be employed to distribute a low-speed clock that is derived from a high-speed clock. This distribution of a low-speed clock enables the scheduling of events in various parts of the SOC ASIC. These events may then be collected in an orderly fashion and ultimately re-timed to the high-speed clock. As an example, a collection of high-speed multiplexer channels comprising a set of low-speed parallel inputs, a low-speed reference timing circuit, and a high-speed reference timing circuit might share common low-speed and high-speed reference clocks.
However, timing inaccuracy occurs between the dividers, which timing inaccuracy is a function of the depth of memory (i.e., number of flip-flops) of a divider circuit and propagation delay differences inherent in electrical wiring or transmission lines. The most significant source of error is the accrual of latency differences due to differences in the stored state of the divider circuit outside of the PLL feedback circuit. As system speeds and circuit density increases, these small latency differences may affect SOC ASIC performance.
An example of potential performance limitation is substrate noise. The timing latency differences between sections of the ASIC served by the low-speed distribution network might result in substrate noise that occurs with limited predictability. Thus, SOC events are timed with an unpredictability based on the state differences between the divider circuits. An SOC scheduler of a prior art system might be unable to predict when activity-induced substrate noise will begin and may be scheduling events that ultimately lead to i) excessive jitter of the ground potential and ii) system meta-stability.